Digital-to-analog converter to produce paired control signals in a power supply controller

ABSTRACT

An controller for use in a power supply includes a variable oscillator and a digital-to-analog converter (DAC). The variable oscillator generates a switching signal to control a first switch of the power supply to regulate an output current of the power supply. The variable oscillator sets a duration of an on-time of the switching signal to be inversely proportional to a magnitude of a first analog signal. The variable oscillator also sets a switching period of the switching signal to be inversely proportional to a magnitude of a second analog signal. The digital-to-analog converter (DAC) converts binary digits into the first and second analog signals, such that a sum of the magnitude of the first analog signal and the magnitude of the second analog signal is a fixed value.

RELATED APPLICATIONS

The present application is a continuation of U.S. patent applicationSer. No. 13/117,998, filed May 27, 2011, now pending, which is acontinuation of U.S. patent application Ser. No. 12/642,450, filed Dec.18, 2009, now issued as U.S. Pat. No. 7,978,107. U.S. patent applicationSer. No. 13/117,998 and U.S. Pat. No. 7,978,107 are hereby incorporatedby reference.

BACKGROUND INFORMATION

1. Field of the Disclosure

This invention is related to controllers for power supplies. Inparticular, the invention is related to controllers that control twoparameters of a switching signal that controls a switch in a switchingpower supply.

2. Background

In a typical application, an ac-dc power supply receives an input thatis between 100 and 240 volts rms (root mean square) from an ordinary acelectrical outlet. Switches in the power supply are switched on and offby a control circuit to provide a regulated output that may be suitablefor providing current to light emitting diodes (LEDs) for illumination.The output is typically a regulated dc current, and the voltage at theLEDs is typically less than 40 volts.

An ac-dc power supply that provides regulated current to LEDs typicallymust meet requirements for power factor and efficiency as explainedbelow. Designers are challenged to provide satisfactory solutions at thelowest cost.

The electrical outlet provides an ac voltage that has a waveformconforming to standards of magnitude, frequency, and harmonic content.The ac current drawn from the outlet, however, is determined by thecharacteristics of the power supply that receives the ac voltage. Inmany applications, regulatory agencies set standards for particularcharacteristics of the current that may be drawn from the ac electricaloutlet. For example, a standard may set limits on the magnitudes ofspecific frequency components of the ac current. In another example, astandard may limit the rms value of the current in accordance with theamount of power that the outlet provides. Power in this context is therate at which energy is consumed, typically measured in the units ofwatts.

The general goal of all such standards for the ac current is to reducethe burden on the system that distributes ac power, sometimes called thepower grid. Components of the current at frequencies other than thefundamental frequency of the ac voltage, sometimes called harmoniccomponents, do no useful work, but yet the power grid must have thecapacity to provide them and it must endure losses associated with them.Harmonic components generally distort the ideal current waveform so thatit has a much higher maximum value than is necessary to deliver therequired power. If the power grid does not have the capacity to providethe harmonic components, the waveform of the voltage will drop to anunacceptable value at times that are coincident with the peaks of thedistorted waveform of the current. The most desirable ac current has asingle frequency component that is at the fundamental frequency of theac voltage. Moreover, the waveform of the most desirable ac current willbe in phase with the ac voltage. That is, the peak ac current will occurat the same time as the peak of the ac voltage. The ideal current willhave an rms value that is equal to the value of the power from theoutlet divided by the rms value of the voltage. In other words, theproduct of the rms voltage and the rms current will be equal to thepower from the outlet when the current has ideal characteristics.

Power factor is a measure of how closely the ac current approaches theideal. The power factor is simply the power from the outlet divided bythe product of the rms current multiplied by the rms voltage. A powerfactor of 100% is ideal. Currents that have frequency components otherthan the fundamental frequency of the ac voltage will yield a powerfactor less than 100% because such components increase the rms value butthey do not contribute to the output power. Currents that have only thefundamental frequency of the ac voltage but are not in phase with the acvoltage will also yield a power factor less than 100% because the powerfrom the outlet is reduced when the peak ac current does not occur atthe same time as the peak ac voltage, while the rms value of the currentremains at its ideal minimum value. That is, an ideal ac current that isnot in phase with the ac voltage will yield a power factor less than100%. The fundamental frequency of the ac voltage is typically either 50Hz or 60 Hz in different regions of the world. By way of example, thefundamental frequency of the ac voltage is nominally 60 Hz in NorthAmerica and Taiwan, but it is 50 Hz in Europe and China.

Since the power supply that receives the ac voltage determines thecharacteristics of the ac current, power supplies often use eitherspecial active circuits or special control techniques to maintain a highpower factor. Power supplies that use only ordinary passive rectifiercircuits at their inputs typically have low power factors that in someexamples are less than 50%, whereas a power factor substantially greaterthan 90% is typically required to meet the standards for input current,such as for example the International Electrotechnical Commission (IEC)standard IED 61000-3-2. Although regulatory agencies in some regions mayimpose the standards, manufacturers of consumer equipment oftenvoluntarily design their products to meet or to exceed standards forpower factor to achieve a competitive advantage. Therefore, ac-dc powersupplies for LEDs, for example, typically must include power factorcorrection.

The efficiency of a power supply is a measure of how much of the powerreceived by the power supply is delivered to the output of the powersupply. A power supply that is 100% efficient delivers to the output allthe power it receives at the input. A power supply that is for example80% efficient delivers only 80% of the power it receives to the output,losing 20% of the power it receives. Regulatory agencies usually mandateminimum efficiencies for power supplies under various operatingconditions. The efficiency of a power supply usually has a strongrelationship to the switching frequency. Therefore, power suppliestypically must control the switching frequency to maintain highefficiency.

To provide a regulated output current at high efficiency from a powerfactor corrected ac input, a power supply typically varies both theon-time and the frequency of a switching signal that switches a switch.As such, there is a need for an integrated circuit controller that canvary two control parameters in a precise and coordinated manner at lowcost.

BRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting and non-exhaustive embodiments of the present invention aredescribed with reference to the following figures, wherein likereference numerals refer to like parts throughout the various viewsunless otherwise specified.

FIG. 1 is a block diagram of one example of an ac-dc power supply thatmaintains a high power factor while regulating an output current at highefficiency, in accordance with the teachings of the present disclosure.

FIG. 2 is functional block diagram of a digital-to-analog converter, inaccordance with the teachings of the present disclosure.

FIG. 3 is an example schematic diagram that shows a reference circuit, acurrent source, and a switch, in accordance with the teachings of thepresent disclosure.

FIG. 4 is another example schematic diagram that shows a referencecircuit, a current source, and a switch, in accordance with theteachings of the present disclosure.

DETAILED DESCRIPTION

Methods and apparatuses for implementing a digital-to-analog converterto produce paired control signals in a power supply controller aredisclosed. In the following description, numerous specific details areset forth in order to provide a thorough understanding of the presentinvention. It will be apparent, however, to one having ordinary skill inthe art that the specific detail need not be employed to practice thepresent invention. In other instances, well-known materials or methodshave not been described in detail in order to avoid obscuring thepresent invention.

Reference throughout this specification to “one embodiment”, “anembodiment”, “one example” or “an example” means that a particularfeature, structure or characteristic described in connection with theembodiment or example is included in at least one embodiment of thepresent invention. Thus, appearances of the phrases “in one embodiment”,“in an embodiment”, “one example” or “an example” in various placesthroughout this specification are not necessarily all referring to thesame embodiment or example. Furthermore, the particular features,structures or characteristics may be combined in any suitablecombinations and/or subcombinations in one or more embodiments orexamples. Particular features, structures or characteristics may beincluded in an integrated circuit, an electronic circuit, acombinational logic circuit, or other suitable components that providethe described functionality. In addition, it is appreciated that thefigures provided herewith are for explanation purposes to personsordinarily skilled in the art and that the drawings are not necessarilydrawn to scale.

The schematic diagram of FIG. 1 shows the salient features of oneexample of an ac-dc power supply 100 receiving an ac input voltageV_(AC) 102 that has a substantially sinusoidal waveform with a periodT_(L) that is the ac line period. The example power supply 100 of FIG. 1has an ac input current I_(AC) 104.

In the example power supply of FIG. 1, a full wave bridge rectifier 106produces a dc rectified voltage V_(RECT) 112 that is received by a dc-dcconverter 116. Rectified voltage V_(RECT) 112 is positive with respectto an input return 108. Dc-dc converter 106 has an input current I_(IN)114 that has a pulsating waveform with a period T_(S) that is theswitching period. In the example of FIG. 1, the waveform of thepulsating input current I_(IN) 114 has a triangular shape. The switchingperiod T_(S) is much less than the ac line period T_(L). The switchingperiod T_(S) is the reciprocal of the switching frequency, and the acline period T_(L) is the reciprocal of the ac line frequency. In oneexample, the switching period T_(S) is about 15 microseconds whereas theac line period T_(L) is about 20 milliseconds. In other words, the acline period T_(L) is typically 1000 times greater than the switchingperiod T_(S), so that there are typically 1000 switching periods withinone ac line period.

In the example power supply of FIG. 1, a small capacitor C1 110 acrossthe dc terminals of bridge rectifier 106 provides a low impedance sourcefor the pulses of input current I_(IN) 114. Capacitor C1 110 filters thehigh frequency components of input current I_(IN) 114 such that themagnitude of the ac input current I_(AC) 104 at any instant issubstantially the average of the dc input current I_(IN) 114, theaverage taken over a switching period T_(S). Capacitor C1 110 is smallenough to allow the rectified voltage V_(RECT) 112 to becomesubstantially zero twice in every ac line period T_(L).

Dc-dc converter 116 in the example of FIG. 1 is controlled by acontroller 132 to regulate a substantially dc output current I_(O) 124that produces an output voltage V_(O) 126 at a load 128. Output voltageV_(O) 126 is positive with respect to an output return 130. In oneexample, load 128 is an arrangement of LEDs.

In the example of FIG. 1, the input return 108 is galvanically isolatedfrom the output return 130. Galvanic isolation prevents dc current fromflowing between input and output of the power supply. In other words, ahigh dc voltage applied between an input terminal and an output terminalof a power supply with galvanic isolation will produce substantially nodc current between the input terminal and the output terminal of thepower supply.

Dc-dc converter 116 typically includes at least one switch 118, at leastone coupled inductor 120, and at least one capacitor 122. All standardconverter configurations with pulsating input currents that aretypically used to provide galvanically isolated outputs, such as forexample the flyback converter and for example the many variants of thebuck converter may be realized by an arrangement of switches, coupledinductors, and capacitors represented by the dc-dc converter block 116in the example of FIG. 1.

The various components identified with the functions of the dc-dcconverter 116 and the controller 132 need not be confined to theboundaries suggested by the boxes drawn in the example power supply 100of FIG. 1. The individual components are segregated into easilyidentifiable regions in this disclosure to aid the explanation of theinvention. Therefore, for example, a component such as switch 118 maystill be considered an element of dc-dc converter 116 when switch 118 isphysically located with circuits associated with a different function.For example, switch 118 may be packaged together with bridge rectifier106, or switch 118 may be included with circuits of controller 132 in anintegrated circuit that is manufactured as either a hybrid or amonolithic integrated circuit.

In the example of FIG. 1, controller 132 receives input current sensesignal U_(IN) 134 that is representative of the dc input current T_(IN)114. Controller 132 also receives an output sense signal U_(OSENSE) 136that may be representative of the output current I_(O) 124, outputvoltage V_(O) 126, or a combination of the two. In other examples,controller 132 may receive a signal that is representative of therectified voltage V_(RECT) 112 in addition to the output sense signalU_(OSENSE) 136 and the input current sense signal U_(IN) 134.

Embodiments described in this disclosure may use many techniques tosense the input current I_(IN) 114 as the current sense signal U_(IN)134. For example, the input current may be sensed as a voltage on adiscrete resistor, or a current from a current transformer, or a voltageacross the on-resistance of a metal oxide semiconductor field effecttransistor (MOSFET) when the input current is the same as the current inthe transistor, or as a current from the sense output of a currentsensing field effect transistor (senseFET). Therefore, this disclosurewill omit specific examples of techniques to sense dc input currentI_(IN) 114.

In the example of FIG. 1, a switch 118 included in dc-dc converter 116is responsive to a switching signal (e.g., gate signal 158) receivedfrom controller 132. In the example of FIG. 1, gate signal 158 is alogic signal that may be high or low within a switching period T_(S). Inone example, switch 118 is closed when gate signal 158 is high, andswitch 118 is open when gate signal 158 is low. A closed switch issometimes referred to as being in an on state. An open switch issometimes referred to as being in an off state. In other words, a switchthat turns on closes, and a switch that turns off opens. A switch in anon state may conduct current. A switch in an off state cannot conductcurrent. Switch 118 in the example of FIG. 1 is sometimes referred to asa single pole single throw (SPST) switch. An SPST switch has twoterminals. The pole terminal is coupled to the signal to be switched. AnSPST switch couples the pole terminal to the throw terminal when theswitch is on. Switches of greater complexity may have multiple poleterminals and multiple throw terminals, with the number of throwterminals generally being equal to or greater than the number of poleterminals. It is appreciated that switches of greater complexity may berealized by multiple SPST switches. In the example of FIG. 1, the dcinput current I_(IN) 114 is a pulsating current that is substantiallyzero when gate signal 158 is low.

It is appreciated that input current sense signal U_(IN) 134 and outputsense signal U_(OSENSE) 136 may be any signals that have a knownrelationship to the dc input current I_(IN) 114 and the output currentI_(O) 124, or the output voltage V_(O) 126. In other words, voltage maybe sensed as a current signal, and current may be sensed as a voltagesignal.

Controller 132 includes a response circuit 138 that includes analog anddigital circuits that define the desired response of the gate signal 158to input current sense signal U_(IN) 134 and output sense signalU_(OSENSE) 136. The response circuit 138 may also include an oscillator(not shown) that provides timing signals such as for example a clocksignal 140 that coordinates the operation of other circuits in the powersupply, and also may provide other timing signals not shown in FIG. 1(e.g., a maximum duty cycle signal).

Controller 132 also includes a binary counter 146, a digital-to-analogconverter (DAC) 150, and a variable oscillator 156. Binary counter 146produces logic signals B₀ through B_(n) 148 that represent the binarydigits (bits) of the number of events counted, where B₀ is the leastsignificant bit (LSB) and B_(n) is the most significant bit (MSB). Inthe example of FIG. 1, binary counter 146 receives clock signal 140, acount up signal 142, and a count down signal 144 from response circuit138. In one example, binary counter 146 is an eight bit counter (i.e.,n=7). It is understood that every bit B_(X) has a complement that is thelogical inverse of B_(X) available to circuits within controller 132.For example, binary counter 146 may produce logic signals B₀ throughB_(n) as well as their corresponding complementary logic signals B₀through B_(n) (not shown). In another example, controller 132 includesone or more inverters coupled to binary counter 146 to provide thecomplementary logic signals B₀ through B_(n) in response to logicsignals B₀ through B_(n), respectively.

In the example of FIG. 1, binary counter 146 counts the number of low tohigh transitions of clock signal 140. When the count up signal 142 isasserted in the example of FIG. 1, clock signal 140 increments the countof the counter. When the count down signal 140 is asserted in theexample of FIG. 1, clock signal 140 decrements the count of the counter.

In the example of FIG. 1, DAC 150 converts the binary digits 148 frombinary counter 146 into the paired analog signals U_(TON) 152 and U_(TS)154. The paired analog signals U_(TON) 152 and U_(TS) 154 may bevoltages or currents. Analog signals U_(TON) 152 and U_(TS) 154 arerestricted to have a fixed sum U_(MAX). In algebraic terms,

U _(TON) +U _(TS) =U _(MAX)   (EQ. 1)

Analog signals U_(TON) 152 and U_(TS) 154 are received by a variableoscillator 156. Variable oscillator 156 produces a gate signal 158 thatalternates between high and low values within switching period T_(S) toswitch the switch 118 in dc-dc converter 116.

Variable oscillator 156 responds to the magnitude of analog signalU_(TON) 152 to set the duration T_(ON) of the high value of gate signal158. Variable oscillator 156 responds to the magnitude of analog signalU_(TS) 154 to set the period T_(S) of gate signal 158. Therefore, asingle digital to analog converter (DAC 150) produces paired analogsignals (U_(TON) 152 and U_(TS) 154) in a controller for a power supply.

Variable oscillator 156 may process the paired analog signals U_(TON)152 and U_(TS) 154 independently to produce desired combinations ofT_(ON) and T_(S) that achieve the desired power factor, efficiency, andoutput performance of the power supply. In one example, U_(TON) 152 andU_(TS) 154 are currents. In one example, a current corresponding toU_(TON) 152 may charge a capacitor to a fixed threshold voltage todetermine the duration T_(ON.) In one example, a current correspondingto U_(TS) 154 may charge a capacitor in an oscillator to an upper fixedthreshold voltage and discharge the capacitor to a lower fixed thresholdvoltage to determine the switching period T_(S). Thus, in one examplethe time T_(ON) would be inversely proportional to the magnitude ofU_(TON) 152 whereas the period T_(S) would be inversely proportional tothe magnitude of U_(TS) 154. When the period T_(S) is inverselyproportional to the magnitude of U_(TS), the frequency f_(S) is directlyproportional to the magnitude of U_(TS).

FIG. 2 shows an example of how the paired analog signals U_(TON) 152 andU_(TS) 154 may be produced as currents I_(TON) and I_(TS) respectivelyfrom a single DAC 150 that receives logic signals 148 that represent thebinary digits from a binary counter 146 that produces an output of n+1bits. Current sources 220, 215, 210 and 205 are coupled to a voltagesource 280, and the current sources have magnitudes that are weighted bypowers of 2, with the lowest magnitude I_(B) for current source 220,magnitude twice I_(B) for current source 215, successively doubling themagnitude for each current source such the current source 205 withhighest magnitude has magnitude 2^(n)I_(B) for a counter with n+1 bits.In one example, the counter is an eight bit counter and thus the highestmagnitude of current produced by a single current source may be 128I_(B)(i.e., 2⁷I_(B)). DAC 150 may optionally include a reference circuit(e.g., see reference circuit 305 of FIG. 3) coupled to each of thecurrent sources 205, 210, 215, and 220 to provide a reference for binaryweighting of the currents produced.

Single pole double throw (SPDT) switches 235, 240, 245, and 250 coupledrespectively to current sources 205, 210, 215, and 220 are each switchedby one of the binary digits 148 from binary counter 146. It isappreciated that an SPDT switch is equivalent to two SPST switches thatare coupled at their pole terminals, one switch is on when the otherswitch is off. In the example of FIG. 2, a high value for one of thedigits couples its respective current source to the node 270 such thatall the current from the current source contributes to the currentI_(TS) of the analog signal 154. Conversely, a low value for one of thedigits, (which is a high value for the complement of the digit) couplesits respective current source to the node 265 such that all the currentfrom the current source contributes to the current I_(TON) of the analogsignal 152.

For example, a high value for binary bit B₁ switches SPDT switch 245 toa first position such that the current 2I_(B) from current source 215 isswitched to node 255, contributing to analog signal 154. Conversely, alow value for binary bit B₁ switches SPDT switch 245 to a secondposition such that the current 2I_(B) from current 215 is switched tonode 260, contributing to analog signal 152. Thus, for every number frombinary counter 146, a current proportional to that number contributes toanalog signal 154, while a current proportional to the complement ofthat binary number contributes to analog signal 152.

In the example of FIG. 2, DAC 150 also includes a current source 225that sets a minimum current I_(MINTON) for analog signal 152, and acurrent source 230 that sets a minimum current I_(MINTS) for analogsignal 154.

TABLE 1 B₃ B₂ B₁ B₀ I_(TON) I_(TS) I_(TON) + I_(TS) 0 0 0 0 I_(MINTON) +15I_(B) I_(MINTS) I_(MINTON) + I_(MINTS) + 15I_(B) 0 0 0 1 I_(MINTON) +14I_(B) I_(MINTS) + I_(B) I_(MINTON) + I_(MINTS) + 15I_(B) 0 0 1 0I_(MINTON) + 13I_(B) I_(MINTS) + 2I_(B) I_(MINTON) + I_(MINTS) + 15I_(B)0 0 1 1 I_(MINTON) + 12I_(B) I_(MINTS) + 3I_(B) I_(MINTON) + I_(MINTS) +15I_(B) 0 1 0 0 I_(MINTON) + 11I_(B) I_(MINTS) + 4I_(B) I_(MINTON) +I_(MINTS) + 15I_(B) 0 1 0 1 I_(MINTON) + 10I_(B) I_(MINTS) + 5I_(B)I_(MINTON) + I_(MINTS) + 15I_(B) 0 1 1 0 I_(MINTON) + 9I_(B) I_(MINTS) +6I_(B) I_(MINTON) + I_(MINTS) + 15I_(B) 0 1 1 1 I_(MINTON) + 8I_(B)I_(MINTS) + 7I_(B) I_(MINTON) + I_(MINTS) + 15I_(B) 1 0 0 0 I_(MINTON) +7I_(B) I_(MINTS) + 8I_(B) I_(MINTON) + I_(MINTS) + 15I_(B) 1 0 0 1I_(MINTON) + 6I_(B) I_(MINTS) + 9I_(B) I_(MINTON) + I_(MINTS) + 15I_(B)1 0 1 0 I_(MINTON) + 5I_(B) I_(MINTS) + 10I_(B) I_(MINTON) + I_(MINTS) +15I_(B) 1 0 1 1 I_(MINTON) + 4I_(B) I_(MINTS) + 11I_(B) I_(MINTON) +I_(MINTS) + 15I_(B) 1 1 0 0 I_(MINTON) + 3I_(B) I_(MINTS) + 12I_(B)I_(MINTON) + I_(MINTS) + 15I_(B) 1 1 0 1 I_(MINTON) + 2I_(B) I_(MINTS) +13I_(B) I_(MINTON) + I_(MINTS) + 15I_(B) 1 1 1 0 I_(MINTON) + 1I_(B)I_(MINTS) + 14I_(B) I_(MINTON) + I_(MINTS) + 15I_(B) 1 1 1 1 I_(MINTON)I_(MINTS) + 15I_(B) I_(MINTON) + I_(MINTS) + 15I_(B)

Table 1 illustrates an example relationship between logic signals B₀through B₃, I_(TON) and I_(TS). Although Table 1 illustrates the logicsignals as including 4 bits, any number of bits may be utilizedincluding 1 or more, in accordance with the teachings of the presentdisclosure. As shown in Table 1, as the count represented by logicsignals B₀ through B₃ increases, so too does the magnitude of thecurrent contributing to analog signal I_(TS) 154. Table 1 furtherillustrates that as the count increases, the magnitude of the currentcontributing to analog signal I_(TON) 152 decreases. However, as statedabove, the sum of the analog signals 152 and 154 is a fixed value. Thus,as shown in Table 1, the sum of I_(TON)+I_(TS) remains substantiallyconstant for all values of the binary digits that that are received byDAC 150.

FIG. 3 is an example schematic diagram that shows a reference circuit305, a current source 385, and an SPDT switch 380, in accordance withthe teachings of the present disclosure. Current source 385 is onepossible implementation of current source 215 of FIG. 2. SPDT switch 380is one possible implementation of switch 245 of FIG. 2. FIG. 3 furthershows a reference circuit 305 that is not shown in FIG. 2, but may beincluded in DAC 150. In one example reference circuit 305 couples toeach binary-weighted current source of FIG. 2. All SPDT switchesincluded in DAC 150 may be identical to SPDT switch 380.

In the example of FIG. 3, reference circuit 305 includes p-channelMOSFETs 310, 315, 320, 330 and 335. Transistors 310 and 315 mirror thecurrent I_(REF1) from a first current source 325 into the sourceterminal of transistor 320 to establish a reference voltage on node 375.The reference voltage on node 375 is selected to guarantee operation ofcurrent source 385 under all anticipated conditions. In one example,I_(REF1) is approximately 1 microampere. A second current source 340sets the current I_(REF2) in transistors 330 and 335. In one example,I_(REF2) is approximately 2 microamperes. Transistors 330 and 335 arecoupled in a typical p-channel cascode arrangement that is duplicated inthe arrangement of transistors 345 and 350 to form current source 215and the other binary-weighted current sources in DAC 150.

The physical dimensions of transistors 345 and 350 may be scaled withrespect to transistors 330 and 335 so that the current from currentsource 385 is the desired multiple of current I_(REF2) from the secondcurrent source 340. The scaling of transistors 345 and 350 may includeselecting the length and width of channel regions to provide desiredratios of the drain currents. For example, the physical dimensions oftransistors 345 and 350 are scaled such that current source 385 providesa current substantially equal to 2I_(B). Further scaling of the physicaldimensions of transistors included in the remaining current sources ofDAC 150 may be implemented to achieve the desired binary weighting ofeach current source as shown in FIG. 2.

The scaling of transistors 345 and 350 may, in the alternative or inaddition to, include providing multiple copies of transistors 330 and335 respectively coupled gate-to-gate, drain-to-drain, andsource-to-source to achieve the desired ratios of the drain currents.FIG. 4 is an example schematic diagram that shows reference circuit 305,a current source 405, and SPDT switch 380, in accordance with theteachings of the present disclosure. Current source 405 is one possibleimplementation of current source 215 of FIG. 2. In the example currentsource 405 of FIG. 4, the physical dimensions of transistor 330 aresubstantially the same as the dimensions of transistor 410 and also oftransistor 415. Similarly, the physical dimensions of transistor 335 aresubstantially the same as the dimensions of transistors 420 and 425.However, since the cascode arrangement of transistors 410 and 420 iscoupled in parallel to a substantially identical cascode arrangement oftransistors 415 and 425 (i.e., the respective gates of transistors 410and 415 and the respective sources of transistors 410 and 415 arecoupled together, while the respective gates of transistors 420 and 425and the respective drains of transistors 420 and 425 are coupledtogether), the current provided by current source 405 is scaled tosubstantially 2I_(B). Thus, each current source of DAC 150 may includemultiple transistors of fixed dimensions coupled in parallel to providethe binary weighting shown in FIG. 2.

Referring now to the examples of both FIGS. 3 and 4, p-channel MOSFETs355 and 360 form SPDT switch 380. In the SPDT switch 245 of FIG. 2,binary bit B₁ from binary counter 146 is coupled to the gate 370 ofp-channel transistor 360. In the SPDT switch 245 of FIG. 2, thecomplement of binary bit B₁ from binary counter 146 is coupled to thegate 365 of p-channel transistor 355. When binary bit B₁ at the gate 370of transistor 360 is high to turn transistor 360 off, the complement tobinary bit B1 at the gate 365 of transistor 355 is low to turntransistor 355 on. When binary bit B₁ at the gate 370 of transistor 360is low to turn transistor 360 on, the complement to binary bit B₁ at thegate 365 of transistor 355 is high to turn transistor 355 off. Thus,when binary bit B₁ is high the current from current source 215 isdirected to node 255, and when binary bit B₁ is low the current fromcurrent source 215 is directed to node 260.

The functions of power supply controller 132 are typically realized inan integrated circuit. Therefore, use of a single digital-to-analogconverter to provide two control signals in contrast to the use of twodigital-to-analog converters to provide the same two control signalsreduces the cost of an integrated circuit controller for a power supply.

The above description of illustrated examples of the present invention,including what is described in the Abstract, are not intended to beexhaustive or to be limitation to the precise forms disclosed. Whilespecific embodiments of, and examples for, the invention are describedherein for illustrative purposes, various equivalent modifications arepossible without departing from the broader spirit and scope of thepresent invention. Indeed, it is appreciated that the specific voltages,currents, frequencies, power range values, times, etc., are provided forexplanation purposes and that other values may also be employed in otherembodiments and examples in accordance with the teachings of the presentinvention.

These modifications can be made to examples of the invention in light ofthe above detailed description. The terms used in the following claimsshould not be construed to limit the invention to the specificembodiments disclosed in the specification and the claims. Rather, thescope is to be determined entirely by the following claims, which are tobe construed in accordance with established doctrines of claiminterpretation. The present specification and figures are accordingly tobe regarded as illustrative rather than restrictive.

What is claimed is:
 1. A controller for use in a power supply, the controller comprising: a variable oscillator configured to generate a switching signal to control a first switch of the power supply to regulate an output current of the power supply, wherein the variable oscillator sets a duration of an on-time of the switching signal to be inversely proportional to a magnitude of a first analog signal received by the variable oscillator, and wherein the variable oscillator sets a switching period of the switching signal to be inversely proportional to a magnitude of a second analog signal received by the variable oscillator; and a digital-to-analog converter (DAC) coupled to receive a plurality of logic signals, each logic signal representative of a respective binary digit, wherein the DAC is configured to convert the binary digits into the first and second analog signals, such that a sum of the magnitude of the first analog signal and the magnitude of the second analog signal is a fixed value.
 2. The controller of claim 1, wherein the DAC comprises: a plurality of current sources; and a plurality of single pole double throw (SPDT) switches, wherein each SPDT switch includes a pole terminal, a first throw terminal, and a second throw terminal, wherein the pole terminal is coupled to receive current from a respective current source, the first throw terminal is coupled to provide the current to the first analog signal, and the second throw terminal is coupled to provide the current to the second analog signal.
 3. The controller of claim 2, wherein each SPDT switch is configured to couple its respective current source to provide the current to the first analog signal in response to at least one of the binary digits received by the DAC, and wherein each SPDT switch is further configured to couple its respective current source to provide the current to the second analog signal in response to a complement of the at least one binary digit.
 4. The controller of claim 2, wherein the plurality of current sources are binary-weighted current sources.
 5. The controller of claim 2, wherein each SPDT switch comprises: a first transistor coupled to a respective current source to provide the current to the first analog signal; and a second transistor coupled to the respective current source to provide the current to the second analog signal.
 6. The controller of claim 1, further comprising a binary counter configured to maintain a count and to generate the plurality of logic signals representative of the count in response to a clock signal.
 7. The controller of claim 6, further comprising a response circuit coupled to the binary counter to generate the clock signal and to generate a count up signal and a count down signal in response to an output sense signal that is representative of the output current of the power supply, wherein the clock signal increments the count when the count up signal is asserted and decrements the count when the count down signal is asserted.
 8. The controller of claim 1, wherein the DAC comprises: a first minimum current source coupled to provide a first minimum current to the first analog signal; and a second minimum current source coupled to provide a second minimum current to the second analog signal.
 9. A power supply, comprising: a coupled inductor ; a first switch coupled to the coupled inductor to regulate an output current of the power supply; and a controller coupled to the first switch, the controller comprising: a variable oscillator configured to generate a switching signal to control the first switch, wherein the variable oscillator sets a duration of an on-time of the switching signal to be inversely proportional to a magnitude of a first analog signal received by the variable oscillator, and wherein the variable oscillator sets a switching period of the switching signal to be inversely proportional to a magnitude of a second analog signal received by the variable oscillator; and a digital-to-analog converter (DAC) coupled to receive a plurality of logic signals, each logic signal representative of a respective binary digit, wherein the DAC is configured to convert the binary digits into the first and second analog signals, such that a sum of the magnitude of the first analog signal and the magnitude of the second analog signal is a fixed value.
 10. The power supply of claim 1, wherein the DAC comprises: a plurality of current sources; and a plurality of single pole double throw (SPDT) switches, wherein each SPDT switch includes a pole terminal, a first throw terminal, and a second throw terminal, wherein the pole terminal is coupled to receive current from a respective current source, the first throw terminal is coupled to provide the current to the first analog signal, and the second throw terminal is coupled to provide the current to the second analog signal.
 11. The power supply of claim 10, wherein each SPDT switch is configured to couple its respective current source to provide the current to the first analog signal in response to at least one of the binary digits received by the DAC, and wherein each SPDT switch is further configured to couple its respective current source to provide the current to the second analog signal in response to a complement of the at least one binary digit.
 12. The power supply of claim 10, wherein the plurality of current sources are binary-weighted current sources.
 13. The power supply of claim 10, wherein each SPDT switch comprises: a first transistor coupled to a respective current source to provide the current to the first analog signal; and a second transistor coupled to the respective current source to provide the current to the second analog signal.
 14. The power supply of claim 9, further comprising a binary counter configured to maintain a count and to generate the plurality of logic signals representative of the count in response to a clock signal.
 15. The power supply of claim 14, further comprising a response circuit coupled to the binary counter to generate the clock signal and to generate a count up signal and a count down signal in response to an output sense signal that is representative of the output current of the power supply, wherein the clock signal increments the count when the count up signal is asserted and decrements the count when the count down signal is asserted.
 16. The power supply of claim 9, wherein the DAC comprises: a first minimum current source coupled to provide a first minimum current to the first analog signal; and a second minimum current source coupled to provide a second minimum current to the second analog signal.
 17. The power supply of claim 9, wherein the first switch and the controller are packaged together in an integrated circuit. 